The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having a stack wiring structure.
Owing to the high integration of semiconductor devices, the design rule for elements of semiconductor devices has been reduced. In a highly scaled semiconductor device, distances between a plurality of wirings and a plurality of contact plugs interposed between the plurality of wirings have gradually been reduced, and the number of stacked has wirings increased.
Additional processing due to a refined pattern and stacked wiring structure may worsen damage to a substrate and adversely affect the operating speed and refresh characteristics of the semiconductor device.